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Videos uploaded by user “Synopsys”
CTLE or DFE?
 
05:06
The performance of a SerDes can be judged on its receiver equalization type. View this video to understand the differences between CTLE and DFE, and when each type is preferred.
Views: 12208 Synopsys
Episode 11: Chip Design Flow -- Step 1
 
06:13
In this video Karen presents 7 simple steps of a design flow process are and describes step 1: "specify your chip".
Views: 29201 Synopsys
Power Management Cells
 
03:43
Describes the various special cells that can be used in UPF-enabled advanced low power design.
Views: 5334 Synopsys
UVM-2: UVM Factory
 
08:10
Code reuse is a key consideration in verification. This webisode shows you how to use the UVM factory to construct testbench objects and how to use the UVM factory override mechanism to change the type of object constructed by the UVM factory through either a run-time switch or a method call in the test without modifying the original code where the object was constructed.
Views: 13648 Synopsys
Unleashing SystemVerilog and UVM: Introduction
 
09:09
What are SystemVerilog and UVM all about? Why would you want to adopt them as part of your verification strategy? This webisode gives you an high level overview of why and how SystemVerilog and UVM help you in putting together a highly reusable testbench for your Device Under Test.
Views: 24776 Synopsys
Episode 1: Introduction
 
04:45
This video series is geared towards a non-technical audience that is interested in learning more about the amazing computer chip industry and how chips are designed and manufactured. Technical jargon is not used, and this is not an advertisement of Synopsys products. In these 19 videos you can expect to develop a basic understanding of how chips are made and learn how engineers design them. You will also gain an understanding and appreciation for the incredible electronic design industry. Please post your comments and questions below. Thank you for watching.
Views: 16857 Synopsys
Power Domains
 
04:40
Josefina defines the concept of a power domain and explains how to properly partition. She also offers guidance on the criteria for deciding whether, and how many, power domains should be used.
Views: 5848 Synopsys
Episode 5: The Switch and Other Parts
 
07:08
This video explains the beginning stages of making a computer chip including its 3 basic elements. Karen also simplifies what a chip is by explaining how it is merely a switch made out of silicon. In the upcoming videos Karen will show how a chip is made in 14 easy steps.
Views: 4978 Synopsys
Episode 6: How a Chip is Made -- Steps 1 - 3
 
04:17
This video covers steps 1-3 of how a chip is made including: • Grow a giant crystal of sand (silicon) • Slice it up into round wafers and polish them • Coat a wafer with a photographic chemical that hardens when exposed to light
Views: 7959 Synopsys
Episode 9: Types and Functions of Chips
 
08:16
In this video Karen goes over the 3 main kinds of chips: analog, digital and FPGAs She also describes how to tell what a chips does as well as explains what a logic gate is and gives an example of how they work.
Views: 5871 Synopsys
Episode 14: Chip Design Flow -- Steps 5 - 6
 
05:16
In this video Karen goes over steps 5-6 of a design flow: • "Blueprint" your chip • Double-check your blueprint
Views: 6750 Synopsys
UVM-3: UVM Reporter
 
09:15
Report message management is a critical part of any verification simulation. In this webisode, you will see how the UVM reporter mechanism help you in managing the report messages in terms of severity, verbosity and simulation action with simple run-time switches without having to recompile any code.
Views: 6616 Synopsys
UPF Supply Sets 1- Introduction
 
02:52
Compared to UPF Supply-Nets, Supply-Sets flow comes with many important features which are central in enabling simplified approach and faster Turn-Around-Time. This video series is targeted to Design-Engineers who are using ‘Supply-Net’ flows. These short videos should help them to learn the Supply-Set concepts (with examples) and equip them to easily migrate to ‘Supply-Sets’ flow.
Views: 4800 Synopsys
Understanding SRIS in PCIe Systems
 
03:23
Learn how and why spread spectrum clocking (SSC) is important to high-speed SerDes design. High-quality IP can include optimized SSC with no impact to CDR.
Views: 5408 Synopsys
Understanding MIPI
 
06:27
This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Views: 29220 Synopsys
Voltage Areas
 
02:02
Josefina describes how the "power domain" UPF logical construct is translated to its physical representation, called a voltage area.
Views: 4342 Synopsys
How to Integrate AXI VIP into a UVM Testbench
 
03:32
VIP manager Tushar Mattu of Synopsys describes how best we can integrate AXI VIP into a UVM Testbench
Views: 3700 Synopsys
UVM-1: UVM Basics
 
09:11
In order to understand UVM, you must first understand the basic feature set of UVM. This webisode gives you a high level view of the four service mechanisms provided by UVM to help you reduce your coding efforts when putting together a verification testbench.
Views: 20065 Synopsys
Reducing EMI in SerDes PHYs using Spread Spectrum Clocking
 
03:25
Learn what spread spectrum clocking (SSC) is and why it is important to high-speed SerDes design.
Views: 2010 Synopsys
Episode 16: Chip Design Flow -- Step 7 (more)
 
05:58
This video continues the previous step 7 of a design flow. Karen describes the problem that arose when chips become so small that light was too big to fit through the stencils and the cost-effective solution that electronic design came up with.
Views: 5146 Synopsys
Episode 12: Chip Design Flow -- Steps 2 - 3
 
02:57
In this video Karen goes over steps 2-3 of a design flow: • Generate the gates • Make the chip testable
Views: 10914 Synopsys
SV-2: The Power of Randomization
 
07:43
The most important feature of SystemVerilog Object-oriented programming is randomization. This webisode will quickly take you through the basics of defining and controlling the randomization of objects to enable you to verify your device as completely as possible.
Views: 10610 Synopsys
Episode 8 Part 1 -- Steps 8 -10
 
05:06
This video covers steps 8-10 of how a chip is made including: • Cut up the wafer into many square chips • Glue the chip into a protective package • Connect the chip to the pins of the package with tiny gold wires Karen will also show how chips connect to the outside world.
Views: 5225 Synopsys
Episode 4: Electronics Everywhere
 
11:39
In this video Karen covers why the electronic design industry is so cool and what products have chips in them. You will also learn how big the chip and electronic design industries are in terms of dollars as well as the global market and challenges they face.
Views: 6193 Synopsys
Synopsys - IP/Hardware
 
01:39
Synopsys is a global leader in electronic design automation, based in Silicon Valley, California, and offering tremendous challenge and opportunity to technology, IT and corporate support professionals. For programmers, designers, engineers and other technological professionals, Synopsys offers the opportunity and challenge of helping design the next generation of technology. The work done here is several years ahead of the curve, as Synopsys designs chips that helps its large, global clients accelerate their innovation. It's a rare opportunity to also accelerate your career while working in a great and flexible work culture, with a tremendously talented team.
Views: 6242 Synopsys
Introduction: Easiest Path to Low Power
 
03:15
This video is the first in the series. In this video, Josefina gives an overview of low power as a costraint, as well as highlights what will be covered in the series.
Views: 2757 Synopsys
Episode 15: Chip Design Flow -- Step 7
 
02:22
This video begins step 7, the last step in a design flow: turn your design into silicon, a physical chip. Karen explains how large the data files for a chip design can be, and this will boggle your mind.
Views: 5576 Synopsys
FSDB Dumping
 
06:54
Synopsys Verdi® supports an open file format called Fast Signal Database (FSDB), which stores the simulation results in an efficient and compact format. Synopsys provides a set of object and support files in the Verdi package that can be linked with popular simulators to extend the simulator command set to support dumping FSDB files directly during simulation. This training video summarizes the essential steps to enable FSDB dumping. The following topics are covered: • Fast Signal Database (FSDB) • Dump FSDB with VCS • Dumping Methods • Frequently-Used Dumping Tasks For more information on Synopsys debug solutions, visit: https://www.synopsys.com/debug
Views: 4598 Synopsys
Working at Synopsys
 
03:13
Synopsys is a global leader in electronic design automation, based in Silicon Valley, California, and offering tremendous challenge and opportunity to technology, IT and corporate support professionals. This video demonstrates the leadership role Synopsys plays in accelerating technology around the world, as well as the culture of solid growth, professionalism and integrity the company offers in what is still startup, teamwork atmosphere. From engineering to programming, design, R&D and support, Synopsys provides unparalleled opportunity to learn, grow and be on the cutting-edge of technology.
Views: 12706 Synopsys
Episode 13: Chip Design Flow -- Step 4
 
10:14
In this video Karen describes step 4 of a design flow: ensure the gates will work
Views: 10095 Synopsys
World’s First USB 3.2 Demonstration
 
02:31
Join Eric Huang and Gervais Fong as they demonstrate the world’s first USB 3.2 host and device IP communicating at USB 3.2 speeds over a standard USB Type-C cable. Learn more about how Synopsys DesignWare USB IP can help bring your products to market at https://www.synopsys.com/usb
Views: 27902 Synopsys
Static Code Analysis: Scan All Your Code For Bugs
 
19:05
Dr. Jared DeMott of VDA Labs continues the series on bug elimination with a discussion of static code analysis. Covered in this talk are a discussion of pattern matching, procedural, data flow, and statistical analysis. Also included are examples of common software vulnerabilities such as memory corruption, buffer overflow and over reads, script injection, XSS and CSRF, command injection, and misconfigurations.
Views: 7930 Synopsys
Power Intent
 
03:12
This video defines the concept of power intent and the Unified Power Format (UPF) language used to describe it.
Views: 2552 Synopsys
Episode 2: Some History
 
11:44
In this video Karen Bartleson goes through some interesting facts about the history of computers, chips, and electronics overall. Karen also explains Moore's law and the background behind it.
Views: 10851 Synopsys
Episode 17: Chip Design Flow -- Step 7 (even more)
 
02:47
Step 7 of a design flow is concluded in this video. Karen explains what it means when an engineer "signs off" on a design and how the manufacturer takes over from there.
Views: 4286 Synopsys
Interactive Debug with Verdi
 
05:45
Verdi Interactive Debug is a technology that allows you to setup the simulation environment and bring the Interactive Mode up easily to debug SVTB in Verdi. Verdi Interactive Mode provides the following advantages: • Simulation control commands to operate simulation execution • Managing Breakpoints for managing the setting and usage of breakpoints • Stack and Thread View frames for viewing the call stack and executed threads • Watch and Local frames for checking signals, member data, and program variables • Class browser and object browser for viewing the member data of class and dynamic objects • Save and Restore session for the convenience of continuing the debug job This video will help you further understand how to use Verdi in Interactive mode. For more information on Synopsys debug solutions, visit: https://www.synopsys.com/debug
Views: 5839 Synopsys
SV-1: Object-oriented programming for designers
 
07:59
If you are a digital design engineer working with Verilog or VHDL and are stumped by Object-oriented programming this is the webisode for you. You will see the connection between Verilog module and classes to enable you to use the full power of Object-oriented programming (OOP) to define, run and debug SystemVerilog and UVM based Testbenches.
Views: 18031 Synopsys
UPF Supply Sets 3 - Availability, Association & Refinement
 
04:17
Compared to UPF Supply-Nets, Supply-Sets flow comes with many important features which are central in enabling simplified approach and faster Turn-Around-Time. This video series is targeted to Design-Engineers who are using ‘Supply-Net’ flows. These short videos should help them to learn the Supply-Set concepts (with examples) and equip them to easily migrate to ‘Supply-Sets’ flow.
Views: 1691 Synopsys
UPF Supply Sets 4 –  Example : Flat & Hierarchical Flows
 
04:59
Compared to UPF Supply-Nets, Supply-Sets flow comes with many important features which are central in enabling simplified approach and faster Turn-Around-Time. This video series is targeted to Design-Engineers who are using ‘Supply-Net’ flows. These short videos should help them to learn the Supply-Set concepts (with examples) and equip them to easily migrate to ‘Supply-Sets’ flow.
Views: 2670 Synopsys
Data Preparation for Verdi
 
07:41
The data preparation for Synopsys Verdi® includes the KDB (Static Design Database), and the FSDB (Dynamic Simulation Database). This video introduces the simplest way to generate FSDB and KDB, and illustrates how to start Verdi to debug them. This video will help you understand: 1. The simplest way to generate FSDB from VCS. 2. How to use UFE (Unified Front-End) to generate KDB, which means to generate both simulation data (simv.daidir) and debug data (KDB) in one step. 3. How to import the design and the FSDB into Verdi. For more information on Synopsys debug solutions, visit: https://www.synopsys.com/debug
Views: 4957 Synopsys
Synopsys Demonstrates MIPI Camera and Display Prototyping System
 
03:35
Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution.
Views: 2661 Synopsys
SV-3: The Power of Inheritance
 
08:24
If randomization is the right hand of verification using SystemVerilog, inheritance is the left hand. This webisode will enlighten you on what inheritance means in OOP, and how it easily enables you to create different tests for verification without affecting other users of the verification environment on your team and without having to change your existing tests and test environments.
Views: 7864 Synopsys
Street Lighting Design & Optimization in LightTools
 
03:11
To learn more about LightTools, please visit https://www.synopsys.com/optical-solutions/lighttools.html LightTools is a complete 3D optical engineering and design software product that supports virtual prototyping, simulation, optimization, and photorealistic renderings of illumination applications. This video demonstrates how LightTools can help you design and optimize high-performance, cost-effective street lighting systems. Highlights include the LightTools Optimization Module, which automatically improves the performance of virtually any type of illumination system, and the LightTools Street Lighting Utility, which can quickly evaluate luminance and illuminance on roadway surfaces and compare results to standard specifications.
Views: 12868 Synopsys
DesignWare IP for PCI Express 4.0 Lane Margining
 
06:04
This demonstration shows the lane margining feature of the DesignWare® IP for PCI Express® 4.0 as defined in the latest specification, allowing system designers to assess performance variation tolerance for design robustness.
Views: 3735 Synopsys
Equalization: Manual or Adaptive?
 
03:26
Understand what adaptive equalization is and how it relates to CTLE or DFE equalization in a PHY.
Views: 7471 Synopsys
Cool Things You Can Do with Verdi - Introduction
 
05:32
In this video we'll show you how to launch Verdi Coverage and analyze your functional and code coverage results from your regression to quickly identify coverage holes.
Views: 13806 Synopsys
Scope
 
03:33
In this video, Josefina explains the concept and usage of scope in UPF power intent. She gives examples of how to define power intent with respect to various scopes in a design.
Views: 2202 Synopsys
UPF Supply Sets 2 –  Supply Set Handles
 
04:31
Compared to UPF Supply-Nets, Supply-Sets flow comes with many important features which are central in enabling simplified approach and faster Turn-Around-Time. This video series is targeted to Design-Engineers who are using ‘Supply-Net’ flows. These short videos should help them to learn the Supply-Set concepts (with examples) and equip them to easily migrate to ‘Supply-Sets’ flow.
Views: 2421 Synopsys
Incrementally Trace in Schematic View
 
06:12
This video will help you further understand how to use the Schematic View to debug complex design logics. The Schematic View is a useful feature in Synopsys Verdi® that helps the users to understand the design logic graphically. The default Schematic View provides an intuitive way to traverse the complete design hierarchically. However, when debugging a complex netlist, sometimes the default Schematic View may look a little complex since it includes all the gates in the opened scope. In this case, Verdi provides different schematic views to address different kinds of debug requirements. The Hierarchical Flatten View is a specific schematic view, which lets the users to start from an empty view, and debug complex logics incrementally. The Hierarchical Flatten View can also show the scope boundaries for the flatten gates, so that users can easily understand where the signal is from and how many scopes it drives. For more information on Synopsys debug solutions, visit: https://www.synopsys.com/debug
Views: 1978 Synopsys
Synopsys Automotive Solutions Overview
 
02:49
This video provides a high-level overview of the various automotive solutions from Synopsys. For more information, please visit: http://www.synopsys.com/automotive
Views: 2549 Synopsys